A comprehensive course that teaches System on Chip design verification concepts and coding in SystemVerilog Language
Free tutorial
4.3
Created by Ramdas Mozhikunnath M
English
What you’ll learn
- Learn the important concepts in SOC/ASIC/VLSI design verification flow
- Learn the System Verilog language for Functional Verification usage
- Be ready and qualified for a Verification job in semiconductor industry
- Udemy Certification on successful course completion
- Be able to code, simulate and verify SystemVerilog Testbenches
Requirements
- Basic digital design or awareness to chip design flows
- Passion for learning
Description
This course introduces the concepts of System on Chip Design Verification with emphasis on Functional Verification flows and methodologies. The course also teaches how to code in SystemVerilog language – which is the most popular Hardware Description Language used for SOC design and verification in semiconductor industry. The course is organised into multiple sections and each uses short video lectures to explain the concepts. After every few other lectures -lab exercises are provided and students will be guided to practically code, simulate and verify using a free browser based Simulator and Waveform viewer. Quizzes are also added to test the students knowledge and progress.
Part 2 of the course covering advanced and industry standard verification methodologies like OVM//UVM will follow based on feedback on this course
Who this course is for:
- Students of VLSI, Digital and Embedded System Design, Microelectronics who wants to be ready for a job in semiconductor industry
- Digital Design and Verification Professionals who are passionate about continuous learning
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Course content
9 sections • 35 lectures • 4h 15m total lengthCollapse all sections
Welcome to Course – Introduction3 lectures • 9min
- Introduction and Overview04:15
- Introduction to SOC and VLSI design flows05:00
- Course Resources1 page
- Testing Awareness before we start4 questions
Verification Concepts Explained5 lectures • 52min
- Verification – What, Why and How ?07:23
- Verification – Planning, Approaches, Metrics09:17
- Verification Methodologies – Simulation, Formal, Assertions13:57
- Directed vs Constrained Random Verification – Coverage12:59
- Other Trends – HW+SW Verification, Emulation08:14
- Test your Verification Concepts now5 questions
Introduction to System Verilog Language5 lectures • 43min
- History and Language usage overview06:20
- Language Constructs – Data types and Operators10:41
- Language Constructs – Loops and Control Flows06:59
- Tasks and Functions05:06
- Arrays and Queues13:53
- Test Your System Verilog Language Basics now5 questions
Basic SV TB – Connecting to your design4 lectures • 20min
- Interfaces08:40
- Clocking Blocks05:26
- Program Blocks06:16
- Direct Programming Interface (DPI)4 pages
- Test – How much more you know now !4 questions
SV – OOP concepts and Randomization5 lectures • 48min
- Basic OOP Concepts07:34
- System Verilog Classes Explained15:01
- Virtual Interfaces07:35
- Random Constraints and usages – Part 109:42
- Random Constraints – Part 208:00
- Test – What have you learned more now ?5 questions
Threads and Inter Process Communication3 lectures • 22min
- Processes and Threads in System Verilog06:22
- System Verilog Mailboxes06:50
- Synchronization – Events and Semaphores08:45
- Test your knowledge now on Advanced System Verilog4 questions
Project Assignment – Building a Testbench for Ethernet Switch6 lectures • 9min
- Exercise 1: Case Study on a Design to be verified09:08
- Exercise 2: Coding exercise to build a Design to be Verified OR Review example5 pages
- Exercise 3: Coding Interfaces and Clocking Blocks to connect2 pages
- Exercise 4: Building Class based Testbench components7 pages
- Exercise 5: Connecting all TB components using mailboxes7 pages
- Exercise 6: Build the top TB with DUT, compile and simulate6 pages
Introduction to Verification Methodologies2 lectures • 15min
- Standard Verification Methodologies – Need and evolution08:17
- Introduction to concept of OVM and UVM06:15
Course Wrapup and Summary2 lectures • 5min
- Summary and learnings and future topics04:50
- Course Improvement Survey00:21
- Final Test – Are you ready for a Verification Job now?2 questions
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